The invention refers to an integrated memory device and to a method for the manufacture thereof. Integrated memory devices comprise a memory array with a plurality of memory cells connected to first and second conductive lines usually called bitlines and wordlines. The memory cells may be volatile or non-volatile memory cells. Volatile memory cells require repeated refreshing of the stored information whereas non-volatile memory cells enable permanent storage of digital information. Non-volatile memory cells for instance may comprise floating gate transistors. Another kind of non-volatile memory cell are NROM cells (nitride read only memory). NROM cells comprise a charge-trapping layer like a silicon nitride layer sandwiched between two opposed dielectric layers. The stack of layers formed thereby represents the gate oxide disposed on a channel region between two source/drain-regions. High energy charge carriers may be scattered into the silicon nitride layer close to one of the source/drain regions upon transistor channel formation. The scattered charge carriers (electrons or holes) remain stored in the silicon nitride layer in locally bound positions. Accordingly an NROM cell may store at least one bit at each lateral end close to the respective source/drain region, further bits being storable in case of multi-level cells controlling the amount of electrical charges by means of the magnitude of electrode voltages applied.
Flash memory devices comprise memory cells being individually programmable but being erasable only commonly within the respective sector of memory cells. The memory array of a flash memory device comprises a plurality of sectors. When an erase operation is performed, all memory cells of one or more sectors are simultaneously erased. On the other hand, flash memory devices comprise memory arrays of comparatively high density of memory cells per substrate surface area. Each NROM transistor cell includes a portion of a charge-trapping layer capable of storing two or more digital information. The charge-trapping layer stack forms part of the gate stacks which further comprise, at least, a first gate conductor layer.
The gate stacks are formed by first depositing and patterning a first stack of layers containing an ONO layer (oxide-nitride-oxide) and at least the first gate conductor layer. Thereby a plurality of patterned line structures extending along a first direction parallel to one another is formed. Subsequently, bitlines are formed in the substrate between the patterned line structures. Conventionally the bitlines are constituted by dopant implanted into the substrate, the dopants forming diffusion bitlines reaching, in lateral direction, closed to the ONO-stack of the patterned line structures. Accordingly, the patterned line structures are used as a mask for implantation of the dopants for the bitlines (that is the source/drain regions) into the substrate. Conventionally, after filling the spaces between the patterned line structures with dielectric material, further layers are deposited and patterned, thereby forming the wordlines. Patterning includes etching through the patterned line structures, thereby forming trenches extending along a second direction perpendicular to the first direction. Thereby wordlines extending perpendicular to the bitlines are formed. Furthermore, the patterned line structures are cut through during patterning as to obtain a plurality of gate stacks of approximately quadratic contour in lateral direction. Thereby each patterned line structure formed prior to bitline implantation is patterned to obtain a plurality of gate stacks.
Whereas the wordlines are highly conductive due to metal layers deposited above the gate stacks, the buried diffusion bitlines have a somewhat increased ohmic resistance compared to the wordlines due to the circumstance that the doped diffusion region in the silicon substrate is less conductive than a metal layer. Though in principle the concentration of dopants in the diffusion lines arranged between the gate stacks might be increased, with view to subsequent thermal treatment steps the allowable maximum dopant concentration in the substrate is limited.
As a consequence of the increased ohmic resistance of the diffusion bitlines compared to the wordlines, the number of memory cells reliably controllable per bitline is limited. It would be desirable to increase the number of memory cells connectable to and reliably operable by a bitline. Therefore the conductivity of the bitline must be increased.
In principle it would be possible to deposit a metal layer between the patterned line structures on those substrate surface portions where the diffusion bitlines are provided. However, at the interface surface between a metal layer and the semiconductor substrate surface a Schottky contact would be formed that would shift the electrical potential of the source/drain regions compared to the bitline potential. Furthermore, many metals tend to form a metal silicide during heat treatment steps performed in the manufacture of the semiconductor device, for instance in order to diffuse the implanted dopants. Often temperatures above 600° C. are required for sufficient heat treatment effects. At such high temperatures many metal suicides are subject to a phase transition, thereby physically changing the microscopic crystal lattice of the respective metal silicide material. Due to the phase transition of the metal silicide, the electric contact between the metal layer and the diffusion line is further deteriorated. These effects undermine the intention of increasing the bitline conductivity.
It would be useful to increase the conductivity of bitlines in integrated memory devices, thereby enabling reliable control of a larger number of memory cells per bitline. It would also be useful to overcome the drawback of silicide formation in bitlines comprising a diffusion line and a further line of a higher conductivity compared to the diffusion line. It might also be useful to provide an integrated memory device and a process of manufacture thereof, which allow easier control of the source/drain region potentials by means of the bitline potential.